|4/2011 - 16|
Accelerating Solution Proposal of AES Using a Graphic ProcessorTOMOIAGA, R. D. , STRATULAT, M.
|Click to see author's profile in SCOPUS, IEEE Xplore, Web of Science|
|Download PDF (542 KB) | Citation | Downloads: 1,368 | Views: 3,558|
AES, benchmark, cryptography, CUDA, GPU
encryption(7), link(6), implementation(6), hardware(6), systems(5), security(5), cuda(5), wseas(4), tomoiaga(4), processing(4)
No common words between the references section and the paper title.
About this article
Date of Publication: 2011-11-30
Volume 11, Issue 4, Year 2011, On page(s): 99 - 104
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2011.04016
Web of Science Accession Number: 000297764500016
SCOPUS ID: 84856612043
The main goal of this work is to analyze the possibility of using a graphic processing unit in non graphical calculations. Graphic Processing Units are being used nowadays not only for game engines and movie encoding/decoding, but also for a vast area of applications, like Cryptography. We used the graphic processing unit as a cryptographic coprocessor in order accelerate AES algorithm. Our implementation of AES is on a GPU using CUDA architecture. The performances obtained show that the CUDA implementation can offer speedups of 11.95Gbps. The tests are conducted in two directions: running the tests on small data sizes that are located in memory and large data that are stored in files on hard drives.
|References|||||Cited By «-- Click to see who has cited this paper|
| Atanasiu A. - Secret Sharing Schemes, capitol in Informatics Security Handbook, vol 2 (Ivan I., C. Toma eds), Editura ASE, 2007.
 Atanasiu, A. - Securitatea informaþiei, vol. 1 (Criptografie), Ed. Infodata, Cluj, 2007.
 Biagio A. D., Barenghi A., Agosta G., Pelosi G., "Design of a parallel AES for graphics hardware using the CUDA framework,"in Proceedings of the 2009 IEEE International Symposium on Paral-lel&Distributed Processing, 2009, pp. 1-8.
 Bielecki W., Burak D., "Parallelization of the AES Algorithm", Proceedings of the 4th WSEAS International Conference on Information Security, Communications and Computers, pp. 224-228, Tenerife, 2005
 Bos J. W., Osvik D.A., Deian S., "Fast Implementation of AES on Various Platforms", SPEED-CC -- Software Performance Enhancement for Encryption and Decryption and Cryptographic Compilers, 2009, Berlin, ICT-2007-216676
 Brokalakis A., Michail H., Kakarountas A., Milidonis A., Goutis C., "A High-Speed and Area Efficent Hardware Implementation of AES-128 Encryption Standard" Proceedings of the 5th WSEAS International Conference on Multimedia, Internet and Video Technologies,pp. 125-129 Corfu, 2005
 R. Cheveresan, S. Holban, "Workload Characterization an Essential Step In Computer Systems Performance Analysis - Methofology and Tools", Advances in Electrical and Computer Engineering, ISSN: 1582-7445, 2009
 P. Chodowiec , K. Gaj, "Very Compact FPGA Implementation of the AES Algorithm", CHES 2003, Proceedings, LNCS Vol. 2779, pp. 319-333, 2003
 D. L. Cook, J. Ioannidis, A. D. Keromytis, and J. Luck, "CryptoGraphics: Secret Key Cryptography Using Graphics Cards", In RSA Conference, Cryptographer's Track (CT-RSA), pp. 334-350, 2005.
 Nvidia CUDA Programming Guide, 2009 , NVIDIA
 Ferguson N., Schneier N., "Practical Cryptography", Wiley Publishing , 2003
 Harrison O., Waldron J., Practical Symmetric Key Cryptography on Modern Graphics Hardware, 17th USENIX Security '08 Symposium, San Jose USA
 Hodjat A., Hwang D., Lai B. C., Tiri K., Verbauwhede I., "A 3.84 Gbits/s AES crypto coprocessor with modes of operation in a 0.18-um CMOS Technology", Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, pages 60--63. ACM, ACM Press, April 2005
 Good T., Benaissa M., "AES on FPGA: from the fastest to the smallest", Proceedings of CHES 2005, pp. 427-440, LNCS 3659, Springer, 2005
 Jacquin L., Roca V., "Parallel arithmetic encryption for high-bandwidth communications on multicore/GPGPU platforms", Proceedings of the 4th International Workshop on Parallel and Symbolic Computation, 2010, Grenoble
[CrossRef] [SCOPUS Times Cited 6]
 Kakarountas A., Michail H., "Implementation of a Cryptographic Co-processor", 6th WSEAS International Conference on Information Security and Privacy, Tenerife, 2007
 Kipper M., Slavkin J., Denisenko D., ," Implementing AES on GPU", University of Toronto, [Online] Available: Temporary on-line reference link removed - see the PDF document
 Lee R.B., Chen Y. Y., "Processor Accelerator for AES" 2010 IEEE 8th Symposium on Application Specific Processors (SASP), 2010
 Luken B., Ouyang M., "AES and DES Encryption with GPU", Proceedings of the ISCA 22nd International Conference on Parallel and Distributed Computing and Communication Systems, pp 67-70,
 Manavski Svetlin, "CUDA Compatible GPU as an efficient Hardware Accelerator for AES Cryptorgraphy", IEEE International Conference on Signal Processing and Communication, ICSPC 2007, pp. 65-68, Nov. 2007
 NVIDIA GeForce 8800GT Characteristics. Hardware Heaven Forum [Online] Available: Temporary on-line reference link removed - see the PDF document
 Parhi K., Zhang X., "An eficient 21.56 Gbps AES implementation on FPGA," in Signals, Systems and Computers. Conference Record of the Thirty-Eighth Asilomar Conference, Nov. 2004, pp. 465-470.
 Urmas Rosenberg, using Graphic Processing Unit in Block Cipher Calculations, Master's Thesis, [Online] Available: Temporary on-line reference link removed - see the PDF document
 Standaert F., Rouvroy G., Legat. J, "Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs", CHES 2003, LNCS Vol. 2779
 Stefanescu G., Arhitectura sistemelor de clacul, curs, 2006 [Online] Available: Temporary on-line reference link removed - see the PDF document
 Takeshi Y., "AES Encryption and Decryption on the GPU", GPU Gems 3, 2007
 Tirtea R., Deconinck G.," Specifications overview for counter mode of operation. Security aspects in case of faults." Electrotechnical Conference, 2004. MELECON 2004. Proceedings of the 12th IEEE Mediterranean, pag. 769-773 Vol.2, 2004.
 Tomoiaga R. D., Stratulat M., "AES Performance Analysis on Several Programming Environments, Operating Systems or Computational Platforms", The Fifth International Conference on Systems and Networks Communications ICSNC 2010, Nice, 2010
 Tomoiaga R. D., Stratulat M., "AES on GPU using CUDA", Proceedings of European Conference for the Applied Mathematics and Informatics EURO-SIAM, Athens, 2010
 Tomoiaga R. D., Stratulat M., "AES algorithm adapted on gpu using cuda for small data and large data volume encryption", International Journal of Applied Mathematics and Informatics, 2011
 Tomoiaga R. D., "Accelerating Solution Proposal of AES using a Graphic Processor", ISSN: 2069-8216, 2011
 Yeom H., Cho Y., Yung M., "High-Speed Implementations of Block Cipher ARIA Using Graphics Processing Units," in Proceedings of the 2008 International Conference on Multimedia and Ubiquitous Engineering (April 24 - 26, 2008). MUE. IEEE Computer Society, Washington, DC, 271-275. 2008.
[CrossRef] [SCOPUS Times Cited 10]
 Zajac P., Grosec O., "Searching for a different AES-Class MixColumns operation", Proceedings of the 6th WSEAS international Conference on Applied Computer Science, Tenerife, 2006.
 [Online] Available: Temporary on-line reference link removed - see the PDF document
 [Online] Available: Temporary on-line reference link removed - see the PDF document
Web of Science® Citations for all references: 0
SCOPUS® Citations for all references: 16 TCR
Web of Science® Average Citations per reference: 0
SCOPUS® Average Citations per reference: 0 ACR
TCR = Total Citations for References / ACR = Average Citations per Reference
We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more
Citations for references updated on 2021-01-15 21:25 in 16 seconds.
Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.