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A Hardware Implementation Of Safe Petri Net ModelsViorica SUDACEVSCHI, Victor ABABII, Valentin NEGURA
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AHDL, FPGA, parallel data processing, Petri Net models hardware implementation, Safe Petri Net
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About this article
Date of Publication: 2006-04-02
Volume 6, Issue 1, Year 2006, On page(s): 54 - 58
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: Not assigned
In this work is proposed a hardware implementation method of Safe Petri Net model (SaPN). The processing structure presents an interaction between homogeny processing elements functional defined. On dependence of interconnections of elements, there can be implemented any complexity of Safe Petri Net model. The processing elements represent a flexible architecture, which permit to adjust them to Safe Petri Net model. Using this architecture and interactions of elements we obtained a reduced time of processing to checking Safe Petri Net to reachability, viability and other behavior properties.
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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